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| THURSDAY, June 10, 2004, 10:30 AM - 12:00 PM | Room: 6B | ||
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TOPIC AREA: NANOMETER ANALYSIS AND SIMULATION | ||
| SESSION 42 | |||
| Panel: Is Statistical Timing Statistically Significant? | |||
| Chair: Andrew B. Kahng - Univ. of California at San Diego, La Jolla, CA | |||
| Organizers: Rich Goldman, Kurt Keutzer | |||
| Process variations that affect critical electrical parameters leading to changes in circuit performance have always posed significant challenges to semiconductor design. In the past, in-die process variation was relatively small, and methods such as corner-based analysis were sufficient. This allowed timing analysis tools to calculate delays and slews in a straightforward way. As statistical variation increases, will corner-casing lead to too much conservatism, or are the advantages of statistical timing analysis overstated? | |||
 42.1 |
Is Statistical Timing Statically Significant? |
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| Speaker(s): | Chandu Visweswariah - IBM Corp., Yorktown Heights, NY Ahsan Bootehsaz - Synopsys, Inc., Mountain View, CA Ed Chen - TSMC, Hsin-Chu, Taiwan Clive Bittlestone - Texas Instruments, Inc., Lou Scheffer - Cadence Design Systems, Inc., San Jose, CA Shekhar Y. Borkar - Intel Corp., Hillsboro, OR | ||
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